Recently, high-density mounting of the electronic components incorporated in the electronics has been developing rapidly along with the demands of a higher performance and miniaturization of electronics. In order to respond to such high-density mounting, a semiconductor chip is often surface mounted on a wiring board in a state of a bear chip, in other words, a semiconductor chip is flip-chip mounted.
As to a wiring board for loading a semiconductor chip, a multilayer wiring board tends to be used, which is suitable for achieving high densification of wiring along with multi-pinning of the semiconductor chip. A semiconductor package having a mounting structure composed of such a semiconductor chip and a multilayer wiring board is further mounted on a mother board so as to constitute a part of a predetermined electronic circuit. As to the mother board as well, a multilayer wiring board, which is suitable for achieving high densification of wiring, is often employed. On the other hand, when examining a semiconductor wafer in which a plurality of semiconductor elements are constructed and a single semiconductor chip, a multilayer wiring board is employed in accordance with the multi-pinning of the element or chip also in a probe card board in which the wafer or chip is loaded.
In flip-chip mounting, generally an underfill agent is applied to fill the space between a wiring board and a semiconductor chip loaded therein. Without the underfill agent to fill in, the reliability of the electrical connection between the wiring board and the semiconductor chip is often low due to the difference in the coefficient of thermal expansion in the in-plane direction between the wiring board and the semiconductor chip. The coefficient of thermal expansion of the semiconductor chips made of a common semiconductor material in the in-plane direction is approximately 3.5 ppm/° C., while the coefficient of thermal expansion of a common wiring board in the in-plane direction in which a glass epoxy board is employed as a core board is 12 to 20 ppm/° C., thus the difference in the coefficient of thermal expansion between the two is relatively large. For this reason, a stress is generated easily in the electrical connection portion between the wiring board and the semiconductor chip loaded therein, due to a change in the ambient temperature or by undergoing a change in the ambient temperature. When at least a predetermined amount of stress is generated in the electrical connection portion, a crack or peeling occurs easily in an interface or the like between a bump of the semiconductor chip and an electrode pad of the wiring board in the connection portion. The underfill agent to fill in the space between the semiconductor chip and the wiring board in flip-chip mounting has a function for relaxing such stress generated in the electrical connection portion. The occurrence of a crack or peeling in the electrical connection portion is suppressed by such a stress relaxation function, whereby connection reliability in flip-chip mounting can be secured.
However, when mounting a large semiconductor chip on a wiring board, sufficient connection reliability often cannot be secured only with the stress relaxation function of the underfill agent. This is because the larger the chip, the more the absolute magnitude of the difference in the thermal expansion between the wiring board and the semiconductor chip becomes, the difference in the thermal expansion being due to the difference in the coefficient of thermal expansion between the wiring board and the semiconductor chip. The larger the difference in the thermal expansion, the larger the stress generated in the electrical connection portion becomes.
Further, when loading a semiconductor wafer or a relatively large semiconductor chip in a probe card and probing and examining the functions thereof, if the difference in the coefficient of thermal expansion between the wafer or chip and the probe card, the electrode of the wafer or chip and the probe pin of the probe card become largely dislocated. As a result, it may not be able to conduct an appropriate testing.
As a means of resolving or diminishing the above-described problems caused by the difference in the coefficient of thermal expansion in the in-plane direction between a wiring board and a semiconductor chip, it is considered to employ a wiring board having a small coefficient of thermal expansion. As the wiring board having a small coefficient of thermal expansion, there has been conventionally known a wiring board in which a metallic material with a low coefficient of thermal expansion is employed as a core board. As the metallic material constituting the metallic core board, generally aluminum, copper, silicon steel, nickel-iron alloy, CIC (copper/invar/cladding material having a laminated structure of copper), or the like is employed. However, since a metallic material is large in its specific gravity to a respectable degree, the weight of a wiring board to be obtained becomes large, thus employing a metallic core board may not be preferred. Moreover, the metallic core board exhibits poor processability in fine processing, thus, for example, it is often difficult to perforate it or make it a thin plate.
On the other hand, as a means of reducing the coefficient of thermal expansion of a wiring board, there has been known a technology where a carbon fiber material is used. Such a technology is disclosed in Japanese Patent Application Laid-Open No. S60-140898, Japanese Patent Application Laid-Open No. H11-40902, and Japanese Patent Application Laid-Open No. 2001-332828.
Japanese Patent Application Laid-Open No. S60-140898 discloses a multilayer wiring board having a multilayer wiring structure in which are alternately laminated copper wiring and a graphite layer as an insulating layer containing a carbon fiber sheet. The coefficient of thermal expansion of a carbon fiber is approximately −1 to 1 ppm/° C. (25° C.) in general, and since the above multilayer wiring board comprises a graphite layer that contains such carbon fiber sheet having a small coefficient of thermal expansion, the coefficient of thermal expansion of the multilayer wiring board is small. According to Japanese Patent Application Laid-Open No. S60-140898, however, the multilayer wiring structure of such a wiring board is formed by means of a so-called “integral lamination technique”. It is known in the integral lamination technique that it is difficult to form a fine multilayer wiring structure and therefore fine pitch electrodes for external connection. For this reason, the wiring board disclosed in Japanese Patent Application Laid-Open No. S60-140898 is not suitable for loading a semiconductor chip in which electrodes for external connection are formed in fine pitch.
Japanese Patent Application Laid-Open No. H11-40902 discloses a multilayer wiring board having a multilayer wiring structure in which are laminated, on both faces of a core board containing a carbon fiber sheet as a base material, carbon wiring and an insulating layer composed of a prepreg containing a glass fiber. Since the core board comprises the carbon fiber sheet, the coefficient of thermal expansion of the wiring board is small. According to Japanese Patent Application Laid-Open No. H11-40902, however, the multilayer wiring structure of such wiring board is formed by means of the integral lamination technique. For this reason, the wiring board disclosed in Japanese Patent Application Laid-Open No. H11-40902 is not suitable for loading a semiconductor chip in which electrodes for external connection are formed in fine pitch.
Japanese Patent Application Laid-Open No. 2001-332828 discloses a wiring board having a laminated structure in which are laminated, on both faces of a core board composed of an insulating layer containing a carbon fiber, copper wiring and an insulating layer composed of a prepreg which does not contain a glass fiber. However, the difference in the coefficient of thermal expansion between the core board composed of the insulating layer containing a carbon fiber and a prepreg which does not contain a glass fiber is large to a respectable degree. If the difference in the coefficient of thermal expansion is large, the core board and the insulating layer are easily separated from each other. When the insulating layer separates from the core board, unreasonable stress acts on the wiring that is formed on the insulating layer, whereby the wiring may be broken. Therefore, according to the technology disclosed in Japanese Patent Application Laid-Open No. 2001-332828, it may be difficult to appropriately create a wiring board having an entirely small coefficient of thermal expansion.